CASE STUDY – Fibrechannel ASIC Design
When a large storage systems vendor decided to develop a Fibrechannel ASIC, the firm turned to Lextel to develop a portion of the chip.
At the time, the highest bit rate contemplated for use on the Firechannel links was 1Gbps ( 1 gigabit per second ). However, the customer’s engineering managers wanted to produce a design that could achieve 4Gbps.
Lextel’s job was to design the FCAL ( Fibrechannel Arbitrated Loop ) portion of the design, which includes the link level interface, including link encoding / decoding ( i.e. 8B10B ), serialization / deserialization, arbitrated loop control, flow control, interfaces to external optical modules and internal higher layers of the protocol.
After reviewing existing FCAL designs from other vendors, and the ASIC technology to be used, Lextel determined that it would not be possible to achieve the customer goal of a 4Gbps bit rate. However, Lextel and the customer still wanted to meet the design goal.
So, Lextel set out to do some ‘out of the box’ thinking. Eventually, we came up with a novel approach to designing the link level encoding and decoding circuitry in order to meet the desired bit rate given the technology in use. The new approach was novel enough that the customer firm engaged Lextel to develop and submit patents to the US Patent and Trademark Office. Ultimately, Lextel generated 10 patent ‘disclosures’ which were consolidated into 4 patent applications which were submitted to and granted by the USPTO.
Lextel continued with the project to perform the overall architecture for the Fibrechannel FCAL section, creation of Functional and Detailed Specifications, detailed design using Verilog, logic synthesis using Synopsis, and logic verification and test bench generation.
We present this case study as an example of Lextel’s ability to meet customer goals even when a straightforward analysis would indicate the goals are very difficult to achieve.
It is often the case that a customer has an aggressive technical, performance, or schedule goal. We strive to use our many years of experience and creativity to meet customer goals. We try to think about engineering problems from many ‘angles’ in order to come up with a great solution that may not be obvious to less experienced engineers.
FCAL Design Tasks Accomplished
- Design Options Analysis
- Critical Risks Analysis
- Novel design approach to meet customer performance goals
- 10 Patent ‘Disclosures’
- 4 Patents Applied for and Granted by USPTO
- System Architecture for section of ASIC
- Functional and Detail Specifications
- Verilog Coding
- Logic Synthesis using Synopsis
- Verification and Test Bench Generation
Background Information on this project
- Fibrechannel Arbitrated Loop
- US Patent 6111528
- LSI Corp (Project ASIC Vendor)
- Synopsys, Inc. (Logic Synthesis Vendor)
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